1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a volatile semiconductor memory device.
2. Description of the Related Art
One type of semiconductor memory device is a dynamic random access memory (DRAM). A DRAM includes memory cells, each of which consists of one access transistor and one capacitor. As is well known, a memory cell stores data in the form of a logic ‘0’ or ‘1’ depending on whether or not an electric charge is stored in the capacitor. One problem associated with DRAMs is that a charge stored in a capacitor may leak out due to various causes. Leaky capacitors cause data stored in a DRAM's memory cell to be lost after a predetermined time period elapses. For example, when the power being supplied to a DRAM is cut-off, any stored data is usually lost when the device remains off for a time period which exceeds the predetermined time period.
That said, even though a DRAM may be cutoff from its power supply, previously stored data may be retained for a few seconds. Provide power is then re-supplied to the DRAM just after it is removed or cut-off, the previously stored data may remain in a memory cell. This may lead to the erroneous output of previously stored data. Accordingly, there is needed a technique that is capable of preventing previously stored data from being read-out when the power supply is re-supplied just after it has been removed or cut-off.